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this is information on a product in full production. april 2014 docid023802 rev 9 1/35 35 ISO8200B galvanic isolated octal high-side smart power solid state relay datasheet - production data features ? parallel input interface ? direct and synchronous control mode ? high common mode transient immunity ? output current: 0.7 a per channel ? short-circuit protection ? channel overtemperature protection ? thermal independence of separate channels ? common output disable pin ? case overtemperature protection ? loss of gnd cc and v cc protection ? undervoltage shutdown with auto restart and hysteresis ? overvoltage protection (v cc clamping) ? very low supply current ? common fault open drain output ? 5 v and 3.3 v ttl/cmos compatible i/os ? fast demagnetization of inductive loads ? reset function for ic outputs disable ? esd protection ? iec 61000-4-2, iec 61000-4-4, iec 61000-4-5 and iec 61000-4-8 compliant applications ? programmable logic control ? industrial pc peripheral input/output ? numerical control machines ? drivers for all types of loads (resistive, capacitive, inductive) description the ISO8200B is a galvanic isolated 8-channel driver featuring a very low supply current. it contains 2 independent galvanic isolated voltage domains (v cc for the power stage and v dd for the digital stage). additional embedded functions are: loss of gnd protection, undervoltage shutdown with hysteresis, and reset function for immediate power output shutdown. the ic is intended to drive any kind of load with one side connected to ground. active channel current limitation combined with thermal shutdown, (independent for each channel), and automatic restart, protect the device against overload and short-circuit. in overload conditions, if junction temperature overtakes threshold, the channel involved is turned off and on again automatically after the ic temperature decreases below a reset threshold. if this condition causes case temperature to reach limit threshold tcr, the overloaded channel is turned off and it only restarts when case and junction temperature decrease down to the reset thresholds. non- overloaded channels continue operating normally. an internal circuit provides an or-wired not latched common fault indicator signaling the channel ovt. the fault pin is an open drain active low fault indication pin. type v demag (1) 1. per channel r ds(on) (1) i out (1) v cc ISO8200B v cc - 45 v 0.11 0.7 a 45 v powerso-36 www.st.com
contents ISO8200B 2/35 docid023802 rev 9 contents 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.1 input signals (in1 to in8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.2 load input data (load ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.3 output synchronization (sync ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1.4 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1.5 output enable (out_en) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 direct control mode (dcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3 synchronous control mode (scm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 fault indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.1 junction overtemperature and case overtemperature . . . . . . . . . . . . . . 22 7 power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.2 thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9 reverse polarity on v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 10.1 supply voltage and power output conventions . . . . . . . . . . . . . . . . . . . . . 29 11 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
docid023802 rev 9 3/35 ISO8200B contents 11.1 thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 12 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 13 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
list of tables ISO8200B 4/35 docid023802 rev 9 list of tables table 1. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. digital supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. diagnostic pin and output protection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. power switching characteristics (v cc = 24 v; -40 c < t j < 125 c) . . . . . . . . . . . . . . . . 12 table 8. logic input and output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. parallel interface timings (v dd = 5 v; v cc = 24 v; -40 c < t j < 125 c) . . . . . . . . . . . . . . . 14 table 10. iec 60747-5-2 insulation characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 table 11. interface signal operation (general) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 12. interface signal operation in direct control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 13. interface signal operation in synchronous control mode . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 14. powerso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 15. footprint data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
docid023802 rev 9 5/35 ISO8200B list of figures list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. r ds(on) measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. dv/dt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 5. td(on)-td(off) synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. td(on)-td(off) direct control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7. watchdog behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. output channel enable timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 9. direct control mode ic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. direct control mode time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. synchronous control mode ic configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12. synchronous control mode time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. multiple device synchronous control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14. thermal status update (dcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 15. thermal status update (scm). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 16. current limitation with different load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 figure 17. thermal protection flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 18. thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 19. reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 20. reverse polarity protection on v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 21. supply voltage and power output conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 22. simplified thermal model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 23. powerso-36 mechanical drawings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 figure 24. footprint recommended data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
block diagram ISO8200B 6/35 docid023802 rev 9 1 block diagram figure 1. block diagram logic sync load out_en in1 in8 vdd power management fault gnddd logic undervoltage detection output clamp current limit junction temperature detection rpd outi case temperature detection vcc clamp vcc gndcc am14889v1
docid023802 rev 9 7/35 ISO8200B pin connection 2 pin connection figure 2. pin connection (top view) table 1. pin description pin name description 1 nc not connected 2v dd positive logic supply 3 out_en output enable 4 sync chip select 5load load input data 6 in1 channel 1 input 7 in2 channel 2 input 8 in3 channel 3 input 9 in4 channel 4 input 10 in5 channel 5 input 11 in6 channel 6 input 12 in7 channel 7 input 13 in8 channel 8 input 14 fault common fault indication - active low 15 gnddd input logic ground, negative logic supply 16 nc not connected
pin connection ISO8200B 8/35 docid023802 rev 9 17 nc not connected 18 nc not connected 19 gndcc output power ground 20 nc not connected 21 out8 channel 8 power output 22 out8 channel 8 power output 23 out7 channel 7 power output 24 out7 channel 7 power output 25 out6 channel 6 power output 26 out6 channel 6 power output 27 out5 channel 5 power output 28 out5 channel 5 power output 29 out4 channel 4 power output 30 out4 channel 4 power output 31 out3 channel 3 power output 32 out3 channel 3 power output 33 out2 channel 2 power output 34 out2 channel 2 power output 35 out1 channel 1 power output 36 out1 channel 1 power output tab tab exposed tab internally connected to vcc, positive power supply voltage table 1. pin description (continued) pin name description
docid023802 rev 9 9/35 ISO8200B absolute maximum ratings 3 absolute maximum ratings table 2. absolute maximum ratings symbol parameter min. max. unit v cc power supply voltage -0.3 45 v v dd digital supply voltage -0.3 6.5 v v in dc input pins, i d and output enable voltage -0.3 +6.5 v v fault fault voltage -0.3 +6.5 v i gnddd dc digital ground reverse current -25 ma i out channel output current (continuous) internally limited a i gndcc dc power ground reverse current -250 ma i r reverse output current (per channel) -5 a i in dc input pins, l d and output enable current -10 + 10 ma i fault fault current -10 + 10 ma v esd electrostatic discharge with human body model (r = 1.5 k ; c = 100 pf) 2000 v e as single pulse avalanche energy per channel not simultaneously @t amb = 125 c, i out = 0.5 a 0.9 j single pulse avalanche energy per channel, all channels driven simultaneously @t amb = 125 c, i out = 0.5 a 0.2 p tot power dissipation at t c = 25 c internally limited (1) 1. protection functions are intended to avoid ic damage in fault conditions and are not intended for continuous operation. continuous or repetitive operat ions of protection func tions may reduce the ic lifetime. w t j junction operating temperature internally limited (1) c t stg storage temperature -55 to 150 c
thermal data ISO8200B 10/35 docid023802 rev 9 4 thermal data 5 electrical characteristics (10.5 v < v cc < 36 v; -40 c < t j < 125 c, unless otherwise specified). table 3. thermal data symbol parameter max. value unit r thj-case thermal resistance, junction-case (1) 1. for each channel. 1.3 c/w r thj-amb thermal resistance, junction-ambient (2) 2. psso36 mounted on the product evaluation board steval-ifp015v2 (fr4, 4 layers, 8 cm 2 for each layer, copper thickness 35 m. 15 c/w table 4. power section symbol parameter test conditions min. typ. max. unit v cc(under)thon v cc undervoltage turn-on threshold 9.5 10.5 v v cc(under)thoff v cc undervoltage turn- off threshold 9v v cc(hys) v cc undervoltage hysteresis 0.35 0.5 v v ccclamp clamp on v cc pin i clamp = 20 ma 45 50 52 v r ds(on) on-state resistance (1) 1. see figure 3. i out = 0.5 a, t j = 25 c i out = 0.5 a t j = 125 c 0.12 0.24 r pd output pull-down resistor 210 k i cc power supply current all channels in off state all channels in on state 5 9 ma ma i lgnd ground disconnection output current v cc = v gnd =0 v v out = - 24 v 500 a v out (off) off-state output voltage channel off and i out = 0 a 1v i out (off) off-state output current channel off and v out = 0 v 5a
docid023802 rev 9 11/35 ISO8200B electrical characteristics table 5. digital supply voltage symbol parameter test conditions min. typ. max. unit v dd(under) v dd undervoltage protection turn-off threshold 2.8 2.9 3 v v dd(hys) v dd undervoltage hysteresis 0.1 v i dd i dd supply current v dd = 5 v and input channel with a steady logic level 4.5 6 ma v dd = 3.3 v and input channel with a steady logic level 4.4 5.9 ma table 6. diagnostic pin and output protection function symbol parameter test conditions min. typ. max. unit v fault fault pin open drain voltage output low i fault = 10 ma 0.4 v i lfault fault output leakage current v fault = 5 v 1 a i peak maximum dc output current before limitation 1.4 a i lim short-circuit current limitation r load = 0 0.7 1.1 1.7 a h yst i lim tracking limits r load = 0 0.3 a t jsd junction shutdown temperature 150 170 c t jr junction reset temperature 150 c t hist junction thermal hysteresis 20 c t csd case shutdown temperature 115 130 145 c t cr case reset temperature 110 c t chyst case thermal hysteresis 20 c v demag output voltage at turn-off i out = 0.5 a; i load > = 1 mh v cc -45 v cc -50 v cc -52 v
electrical characteristics ISO8200B 12/35 docid023802 rev 9 figure 3. r ds(on) measurement table 7. power switching characteristics (v cc = 24 v; -40 c < t j < 125 c) symbol parameter test conditions min. typ. max. unit dv/dt(on) turn-on voltage slope i out = 0.5 a, resistive load 48 - 5.6 - v/s dv/dt(off) turn-off voltage slope i out = 0.5 a, resistive load 48 -2.81- v/s t d (on) turn-on delay time (1) 1. see figure 4 , figure 5 , and figure 6 . i out = 0.5 a, resistive load 48 -1722s t d (off) turn-off delay time (1) i out = 0.5 a, resistive load 48 -2240s t f fall time (1) i out = 0.5 a, resistive load 48 -5-s t r rise time (1) i out = 0.5 a, resistive load 48 -5-s tab vcc v r ds(on) load am14891v1
docid023802 rev 9 13/35 ISO8200B electrical characteristics figure 4. dv/dt figure 5. td(on)-td(off) synchronous mode tf tr dv (on) dv (off) 10% 80% 90% t vout am14892v1 10% 90% 50% td(on) td(off) t sync vout t scm am14893v1 figure 6. td(on)-td(off) direct control mode 10% 90% 50% td(on) td(off) t in(i) vout t dcm am14894v1 table 8. logic input and output symbol parameter test conditions min. typ. max. unit v il logic input, load and out_en low level voltage -0.3 0.3 x v dd v v ih logic input, load and out_en high level voltage 0.7 x v dd v dd +0.3 v v i(hyst) logic input, load and out_en hysteresis voltage v dd = 5 v 100 mv i in logic input, load and out_en current v in = 5 v 10 a t wm power side watchdog time 272 320 400 s
electrical characteristics ISO8200B 14/35 docid023802 rev 9 table 9. parallel interface timings (v dd = 5 v; v cc = 24 v; -40 c < t j < 125 c) symbol parameter test conditions min. typ. max. unit t dis(sync) sync disable time sync. control mode 10 s t dis(dcm) sync load disable time direct control mode 80 ns t w(sync) sync negative pulse width sync. control mode 20 195 s t su(load) load setup time sync. control mode 80 ns t h(load) load hold time sync. control mode 400 ns t w(load) load pulse width sync. control mode 240 ns t su(in) input setup time 80 ns t h(in) input hold time 10 ns t w(in) input pulse width sync. control mode 160 ns direct control mode 20 s t inld in to load time direct control mode from in variation to load f alling edge 80 ns t ldin load to in time direct control mode from load falling edge to in variation 400 ns t w(out_en) out_en pulse width 150 ns t p(out_en) out_en propagation delay 22 40 s t jitter(scm) jitter on single channel sync. mode 6 s t jitter(dcm) direct mode 20 f refresh refresh delay 15 khz
docid023802 rev 9 15/35 ISO8200B electrical characteristics table 10. iec 60747-5-2 insulation characteristics symbol parameter test conditions value unit cti comparative tracking index (tracking resistance) din iec 112/vde 0303 part 1 400 v isolation group material group (din vde 0110, 1/89, table 1 ii v iso isolation voltage per ul 1577 100% production v test = 1.2 x v iso =1644 v, t=1 s 1370 v peak v pr input-to-output test voltage as per iec 60747-5-2 100% production test method b, t m = 1 s partial discharge < 5 pc 1644 v peak characterization test method a, t m = 10 s partial discharge < 5 pc 1315 v peak v iotm transient overvoltage as per iec 60747-5-2 characterization test v test = 1.2 x v iotm , t = 60 s 3500 v peak clr clearance (minimum external air gap) measured from input terminals to output terminals, the shortest distance through air 2.6 mm cpg creepage (minimum external tracking) measured from input terminals to output terminals, the shortest distance path analog body 2.6 mm
functional description ISO8200B 16/35 docid023802 rev 9 6 functional description 6.1 parallel interface smart parallel interface built-in ISO8200B offers three interfacing signals easily managed by a microcontroller. the load signal enables the input buffer storing the value of the channel inputs. the sync signal copies the input buffer value into the transmission buffer and manages the synchronization between low voltage side and the channel outputs on the isolated side. the out_en signal enables the channel outputs. an internal refresh signal updates the configuration of the channel outputs with a f refresh frequency. this signal can be disabled forcing low the sync input when load is high. sync and load pins can be in direct control mode (dcm) or synchronous control mode (scm). the operation of these two signals is described as follows: 6.1.1 input signals (in1 to in8) inputs from in1 to in8 are the driving signals of the corresponding out1 to out8 outputs. data are direct loaded on related outputs if sync and load inputs are low (dcm operation) or stored into input buffer when load is low and sync is high. 6.1.2 load input data ( load ) the input is active low; it stores the data from in1 to in8 into the input buffer. 6.1.3 output synchronization (sync ) the input is active low; it enables the ISO8200B transmission buffer loading input buffer data and manages the transmission between the two isolated sides of the device. table 11. interface signal operation (general) load sync out_en device behavior don?t care don?t care low (1) 1. the outputs are turned off on out_en falling edge and they are kept disabled as long as it is low. the outputs are disabled (turned off) high high high the outputs are left unchanged low high high the input buffer is enabled the outputs are left unchanged high low high the internal refresh signal is disabled the transmission buffer is updated the outputs are left unchanged low low high the device operates in direct control mode as described in the respective paragraph
docid023802 rev 9 17/35 ISO8200B functional description 6.1.4 watchdog the isolated side of the device provides a watchdog function in order to guarantee a safe condition when v dd supply voltage is missing. if the logic side does not update the output status within t wd , all outputs are disabled until a new update request is received. the refresh signal is also considered a valid update signal, so the isolated side watchdog does not protect the system from a failure of the host controller (mcu freezing). figure 7. watchdog behavior 6.1.5 output enable (out_en) this pin provides a fast way to disable all outputs simultaneously. when the out_en pin is driven low the outputs are disabled. to enable the output stage, the out_en pin has to be raised. this timing execution is compatible with an external reset push, safety requirement, and allows, in a plc system, the microcontroller polling to obtain all internal information during a reset procedure. figure 8. output channel enable timing timeout counter out0?out7 refresh any update request resets the watchdog counter if the isolated side does not receive an update request within the watchdog timeout all outputs are turned off ! outputs are kept off until an update request is received don?t care don?t care d0?d7 _____ load don?t care ______ synch vdd a bc a bc skipped c c ipg1912131338lm out_en tw(out_en) outx tp(out_en) t t am14896v1
functional description ISO8200B 18/35 docid023802 rev 9 6.2 direct control mode (dcm) when sync and load inputs are driven by the same signal, the device operates in direct control mode (dcm). in dcm the sync / load signal operates as an active low input enable: ? when the signal is high, the current output configuration is kept regardless the input values ? when the signal is low, each channel input directly drives the respective output this operation mode can also be set shorting both signals to the digital ground; in this case the channel outputs are always directly driven by the inputs except when out_en is low (outputs disabled). figure 9. direct control mode ic configuration table 12. interface signal operation in direct control mode sync / load out_en device behavior don?t care low (1) 1. the outputs are turned off on out_en falling edge and they are kept disabled as long as it is low. the outputs are disabled (turned off) high high the outputs are left unchanged low high the channel inputs drive the outputs vdd vdd gnddd gnd vdd load out_en in1 in2 in3 in4 in5 in6 in7 in8 sync fault vdd mcu iso8200 load out_en vdd vdd in1 in2 in3 in4 in5 in6 in7 in8 gnddd gnd sync fault vdd vdd mcu iso8200 inputs are enabled by mcu through the sync/load signals inputs are always enabled (outputs can be disabled through out_en) gpio gpio am14897v1
docid023802 rev 9 19/35 ISO8200B functional description figure 10. direct control mode time diagram 6.3 synchronous control mode (scm) when sync and load inputs are independently driven, the device can operate in synchronous control mode (scm). the scm is used to reduce the jittering of the outputs and to drive all outputs of different devices at the same time. in scm the load signal is forced low to update the input buffer while the sync signal is high. the load signal is raised and the sync one is forced low for at least t sync(scm) . during this period, the internal refresh is disabled and any pending transmission between the low voltage and the isolated side is completed. when the sync signal is raised the channel output configuration is changed according to the one stored in the input. if the t sync(scm) limit is met, the maximum jitter of the channel outputs is t jitter (scm). if more devices share the same sync signal, all device outputs change simultaneously with a maximum jitter related to maximum delay and maximum jitter for single device. sync load inx outx t inld t ldin t su(in) t h(in) td(off) tf td(on) tr 1/ f refresh internal refresh t ds(dmc) am14898v1
functional description ISO8200B 20/35 docid023802 rev 9 figure 11. synchronous control mode ic configuration table 13. interface signal operati on in synchronous control mode load sync out_en device behavior don?t care don?t care low (1) 1. the outputs are turned off on out_en falling edge and they are kept disabled as long as it is low. the outputs are disabled (turned off) high high high the outputs are left unchanged low high high the input buffer is enabled the outputs are left unchanged high low high the internal refresh signal is disabled the transmission buffer is updated the outputs are left unchanged high rising edge high the outputs are updated according to the current transmission buffer value low low high should be avoided (dcm operation only) vdd vdd gnddd gnd vdd load out_en in1 in2 in3 in4 in5 in6 in7 in8 sync fault vdd mcu iso8200 gpio am14899v1
docid023802 rev 9 21/35 ISO8200B functional description figure 12. synchronous control mode time diagram figure 13. multiple device synchronous control mode t dis (sync) t w (sync) t h (load) t w (load) t su (load) t su (in) t h (in) t w (in) t d (off) t f gipglm3101141151 load ld1 sync ld2 data1..data8 in1..in8 out0..out7 mcu dev1 dev2 sync ld1 ld2 data1..data8 out1..out8 dev1 out1..out8 dev2 8 8 8 x x a a b b sync load in1..in8 out0..out7 sync am14901v1
functional description ISO8200B 22/35 docid023802 rev 9 6.4 fault indication the fault pin is an active low open drain output indicating fault conditions. this pin is active when at least one of the following conditions occurs: ? junction overtemperature of one or more channels (t j >t tjsd ) ? communication error 6.4.1 junction overtemperature and case overtemperature the thermal status of the device is updated during each transmission sequence between the two isolated sides. in scm operation, when the load signal is high and the sync one is low, the communication is disabled. in this case the thermal status of the device cannot be updated and the fault indication can be different from the current status. in any case, the thermal protection of the channel outputs is always operative. figure 14. thermal status update (dcm)
docid023802 rev 9 23/35 ISO8200B functional description figure 15. thermal status update (scm) thermal fault fault internal refresh sync skipped tx/rx tx/rx tx/rx am14992v1
power section ISO8200B 24/35 docid023802 rev 9 7 power section 7.1 current limitation the current limitation process is active when the current sense connected on the output stage measures a current value, which is higher than a fixed threshold. when this condition is verified the gate voltage is modulated to avoid the increase of the output current over the limitation value. figure 16 shows typical output current waveforms with different load conditions. figure 16. current limitation wi th different load conditions
docid023802 rev 9 25/35 ISO8200B power section 7.2 thermal protection the device is protected against overheating in case of overload conditions. during the driving period, if the output is overloaded, the device suffers two different thermal stresses, the former related to the junction, and the latter related to the case. the two faults have different trigger thresholds: the junction protection threshold is higher than the case protection one; generally the first protection, that is active in thermal stress conditions, is the junction thermal shutdown. the output is turned off when the temperature is higher than the related threshold and turned back on when it goes below the reset threshold. this behavior continues until the fault on the output is present. if the thermal protection is active and the temperature of the package increases over the fixed case protection threshold, the case protection is activated and the output is switched off and back on when the junction temperature of each channel in fault and case temperature is below the respective reset thresholds. figure 17 shows the thermal protection behavior, while figure 18 reports typical temperature trends and output vs. input state. figure 17. thermal protection flowchart input in(i) high output (i) on fault(i) off t j(i) >t jsd t c >t csd t c >t cr output (i) off fault(i) on n y y n y n t jr >t j(i) y n am14995v1
power section ISO8200B 26/35 docid023802 rev 9 figure 18. thermal protection
docid023802 rev 9 27/35 ISO8200B reverse polarity protection 8 reverse polarity protection reverse polarity protection can be implemented on board using two different solutions: 1. placing a resistor (r gnd ) between ic gnd pin and load gnd 2. placing a diode between ic gnd pin and load gnd if option 1 is selected, the minimum resistance value has to be selected according to the following equation: equation 1 r gnd v cc /i gndcc where i gndcc is the dc reverse ground pin current and can be found in section 3: absolute maximum ratings of this datasheet. power dissipated by r gnd during reverse polarity situations is: equation 2 p d = (v cc ) 2 /r gnd if option 2 is selected, the diode has to be chosen by taking into account vrrm >|v cc | and its power dissipation capability: equation 3 p d i s *v f note: in normal conditions (no reverse polarity) due to the diode, there is a voltage drop between gnd of the device and gnd of the system. figure 19. reverse polarity protection this schematic can be used with any type of load. r gnd gnd cc output i load diode isolation intput i +vcc +vdd gnd dd gipd2611131255lm
reverse polarity on v dd ISO8200B 28/35 docid023802 rev 9 9 reverse polarity on v dd the reverse polarity on v dd can be implemented on board by placing a diode between gnd dd pin and gnd digital ground. the diode has to be chosen by taking into account vrrm >|v dd | and its power dissipation capability: equation 4 p d i dd *v f note: in normal conditions (no reverse polarity), due to the diode, there is a voltage drop between gnd dd of the device and digital ground of the system. figure 20. reverse polarity protection on v dd r gnd gnd cc output i load diode isolation intput i +vcc +vdd gnd dd diode gipd2611131302lm
docid023802 rev 9 29/35 ISO8200B conventions 10 conventions 10.1 supply voltage and power output conventions figure 21 shows the convention used in this paper for voltage and current usage. figure 21. supply voltage and power output conventions 11 thermal information 11.1 thermal impedance figure 22. simplified thermal model i dd i cc vdd v cc i out v out i fault i in i out_en v dd fault in out_en gnddd gndcc out v cc sync load i sync i load am14997v1 rth1a rth1b rth1h rth2 rthc_a cth tj1 tj2 tj8 am14998v1
package mechanical data ISO8200B 30/35 docid023802 rev 9 12 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. figure 23. powerso-36 mechanical drawings
docid023802 rev 9 31/35 ISO8200B package mechanical data table 14. powerso-36 mechanical data dim. mm min. typ. max. a 3.60 a1 0.10 0.30 a2 3.30 a3 0 0.10 b0.22 0.38 c0.23 0.32 d 15.80 16.00 d1 9.40 9.80 e 13.90 14.50 e1 10.90 11.10 e2 2.90 e3 5.8 6.2 e0.65 e3 11.05 g 0 0.10 h 15.50 15.90 h 1.10 l0.80 1.10 n 10 s0 8
package mechanical data ISO8200B 32/35 docid023802 rev 9 figure 24. footprint recommended data table 15. footprint data dim. mm a9.5 b 14.7-15.0 c 12.5-12.7 d6.3 e0.46 g0.65
docid023802 rev 9 33/35 ISO8200B ordering information 13 ordering information table 16. ordering information order code package packaging ISO8200B powerso-36 tube ISO8200Btr powerso-36 tape and reel
revision history ISO8200B 34/35 docid023802 rev 9 14 revision history table 17. document revision history date revision changes 19-oct-2012 1 initial release. 01-jul-2013 2 updated figure 24: footprint recommended data and table 15: footprint data . 28-oct-2013 3 document status promoted from preliminary to production data. added iec bullet to features. updated table 4 , table 6 , table 7 , and table 9 . deleted table titled: ?insulation and safety-related specifications? and table titled: ?device immunity specifications?. changed table 10: iec 60747-5-2 insulation characteristics changed figure 10 . 12-nov-2013 4 added to table 10 clr and cpg parameters. 29-nov-2013 5 removed v iorm parameter from table 10 . updated section 8: reverse polarity protection . added section 9: reverse polarity on v dd . changed figure 19 . added figure 20 . 24-jan-2014 6 changed figure 7 . added note to table 3 . added test conditions: t j = 125 c to table 4 . added typ. and max. values of i dd to table 5 . added max. values of t d (on) and t d (off) to table 7 . added typ. and max. values of t p(out_en) to table 9 . added t jitter(dcm) value to table 9 . 03-feb-2014 7 updated figure 12 . 06-feb-2014 8 updated figure 12 and table 9 . 22-apr-2014 9 updated eas parameter in table 2 . updated i peak parameter in table 6 . updated mechanical data.
docid023802 rev 9 35/35 ISO8200B please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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